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The entire computing industry has a retentiveness problem, and a new consortium of manufacture partners, dubbed Gen-Z, hopes to solve information technology. For decades, DRAM has driven virtually every segment of the computing market, from smartphones to supercomputers, merely new classes of retentivity devices already threaten that dominance. What'southward needed is a new memory interface that can tie these various components together, and that'south where Gen-Z comes in.

Interface-1

Some of the problems with DRAM performance scaling are long-continuing, well-known problems. Generally speaking, the amount of bandwidth available per cadre has continued to decrease, despite the advent of DDR4. Consider the difference between Intel'due south Cadre i7-6950X, with 10 CPU cores and a total bandwidth of 76.8GB/s when using DDR4-2400 versus the Cadre i7-4960X, with half-dozen cores and 59.7GB/south of DDR3-1866. The total bandwidth bachelor to the Cadre i7-6950X is higher, past nearly 30% — but the 6950X also has 10 cores and 20 threads, compared with the 4960X's six cores and 12 threads. Total bandwidth per cadre has indeed gone downwardly — from ix.95GB/s per core for the 4960X to 7.68GB/s per core for the 6950X.

This difference persists fifty-fifty if nosotros assume the user steps outside Intel's official specs and uses the highest-terminate RAM realistically available. A quad-aqueduct Core i7-4960X with DDR3-3100 would offer 99.2GB/due south of bandwidth (16.5GB/due south of bandwidth per core) while a Core i7-6950X with DDR4-4266 offers 136.51GB/s of bandwidth, or 13.65GB/s per core. No thing which components you cull, the amount of bandwidth available per core is going downwards.

Then instead of only beating our heads confronting that primal limit, Gen-Z wants to beef upwardly the performance of adjacent-generation interconnects that might exist used to tap these emerging types of memory — some of which need to exist connected in means not covered by current standards.

DRAM-SCM

Today, the majority of systems contain DRAM and some type of storage, be that HDD or SSD. That's going to start changing in the not-too-afar future, as High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), and Managed DRAM are all more than widely adopted. Other technologies, like Resistive RAM (RRAM), 3D XPoint (aka Intel's Optane), magnetic RAM (MRAM) and low-latency NAND volition all be deployed in diverse systems and components. The goal of Gen-Z every bit stated is to build a "memory semantic textile" that handles communications as retentiveness operations with sub-microsecond latencies, from the time the CPU issues a load command to the time data is actually stored in a register.

Gen-Z-4

That Gen-Z is talking about sub-microsecond latencies leaves a lot of room for speculation as far as final performance is concerned. DRAM is technically a sub-microsecond memory, merely nosotros typically measure DRAM latency in tens to hundreds of nanoseconds (the exact number depends on the blazon of performance being measured, the DRAM's timing, and the speed of the integrated retentiveness controller on-board the CPU). Gen-Z could offer substantially faster operation for sure kids of attached hardware scenarios than equivalent standards today — particularly when compared with existing interconnect standards, which are often much slower than DRAM.

Gen-Z-3

The long-term goal of Gen-Z is to tie the entire attached ecosystem of products together on a single open standard that can support sub-100ns load-to-use memory latencies in at least some cases. This will be at least partly determined by which type of memory is being discussed, which is probably ane reason why the Gen-Z presentation doesn't contain a lot of hard figures. A number of pregnant companies are backing the initiative, including AMD, ARM, Broadcom, Cray, Dell, HP, Huawei, Micron, Samsung, SK Hynix, and Xylinx.

The one major company missing is one you lot might expect to lead such an endeavor: Intel. With upwardly of 98% of the server and enterprise markets, Intel hardware is what you would look these new retentiveness standards to all exist compatible with. Fifty-fifty if y'all think AMD and ARM are poised to seize significant chunks of the data center market, such growth takes years to build. Enterprise giant Cisco is also nowhere to be constitute. More details and specification data are expected before the finish of the yr, implying this project has already been in the works for quite some fourth dimension.